title: |
A Novel, Efficient Architecture for the 1D, Lifting-Based DWT with Folded and Pipelined Schemes |
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publication: |
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part of series: |
Advances in Intelligent Systems Research | |
ISBN: |
978-90-78677-01-7 | |
ISSN: |
1951-6851 | |
DOI: |
doi:10.2991/jcis.2006.20 (how to use a DOI) | |
author(s): |
Chin-Fa Hsieh, Tsung-Han Tsai, Neng-Jye Hsu, Chih-Hung Lai |
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corresponding author: |
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publication date: |
October 2006 |
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keywords: |
lifting, discrete wavelet transform |
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abstract: |
In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied in the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speed up the clock rate of the DWT. The architecture has been coded in Verilog HDL, then verified successfully by the platform of Quartus-II of version 5.0. Finally, it was realized with the FPGA device of Cyclone family from Altera Corp. |
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copyright: |
©
Atlantis Press. This article is distributed under the
terms of the Creative Commons Attribution License, which permits
non-commercial use, distribution and reproduction in any medium,
provided the original work is properly cited. |
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full text: |