A Novel, Efficient Architecture for the 1D, Lifting-Based DWT with Folded and Pipelined Schemes
- Chin-Fa Hsieh 0, Tsung-Han Tsai, Neng-Jye Hsu, Chih-Hung Lai
- Corresponding Author
- Chin-Fa Hsieh
0China Institute of Technology, Taipei, Taiwan
- https://doi.org/10.2991/jcis.2006.20How to use a DOI?
- lifting, discrete wavelet transform
- In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied in the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speed up the clock rate of the DWT. The architecture has been coded in Verilog HDL, then verified successfully by the platform of Quartus-II of version 5.0. Finally, it was realized with the FPGA device of Cyclone family from Altera Corp.
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- This is an open access article distributed under the CC BY-NC license.
Cite this article
TY - CONF AU - Hsieh, Chin-Fa AU - Tsai, Tsung-Han AU - Hsu, Neng-Jye AU - Lai, Chih-Hung DA - 2006/10/05 TI - A Novel, Efficient Architecture for the 1D, Lifting-Based DWT with Folded and Pipelined Schemes BT - 9th Joint International Conference on Information Sciences (JCIS-06) PB - Atlantis Press SN - 1951-6851 UR - https://doi.org/10.2991/jcis.2006.20 DO - https://doi.org/10.2991/jcis.2006.20 ID - Hsieh2006 ER -