9th Joint International Conference on Information Sciences (JCIS-06)

A Novel, Efficient Architecture for the 1D, Lifting-Based DWT with Folded and Pipelined Schemes

Authors
Chin-Fa Hsieh 0, Tsung-Han Tsai, Neng-Jye Hsu, Chih-Hung Lai
Corresponding Author
Chin-Fa Hsieh
0China Institute of Technology, Taipei, Taiwan
DOI
https://doi.org/10.2991/jcis.2006.20How to use a DOI?
Keywords
lifting, discrete wavelet transform
Abstract
In this paper, we propose a novel, efficient VLSI architecture for the implementation of one-dimension, lifting-based discrete wavelet transform (DWT). Both of the folded and the pipelined schemes are applied in the proposed architecture; the former scheme supports higher hardware utilization and the latter scheme speed up the clock rate of the DWT. The architecture has been coded in Verilog HDL, then verified successfully by the platform of Quartus-II of version 5.0. Finally, it was realized with the FPGA device of Cyclone family from Altera Corp.
Copyright
© The authors.
Open Access
This is an open access article distributed under the CC BY-NC license.

Download article (PDF)

Cite this article

TY  - CONF
AU  - Hsieh, Chin-Fa
AU  - Tsai, Tsung-Han
AU  - Hsu, Neng-Jye
AU  - Lai, Chih-Hung
DA  - 2006/10/05
TI  - A Novel, Efficient Architecture for the 1D, Lifting-Based DWT with Folded and Pipelined Schemes
BT  - 9th Joint International Conference on Information Sciences (JCIS-06)
PB  - Atlantis Press
SN  - 1951-6851
UR  - https://doi.org/10.2991/jcis.2006.20
DO  - https://doi.org/10.2991/jcis.2006.20
ID  - Hsieh2006
ER  -