Proceedings of the 9th Joint International Conference on Information Sciences (JCIS-06)

An Efficient CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphics Rendering

Authors
Tze-Yun Sung 0
Corresponding Author
Tze-Yun Sung
0Dept. of Microelectronics Engineering, Chung Hua University
Available Online October 2006.
DOI
https://doi.org/10.2991/jcis.2006.232How to use a DOI?
Keywords
Redundant CORDIC arithmetic, CORDIC algorithm, 3-D vector interpolation, high-throughput.
Abstract
High performance architectures for the data intensive and latency restrained applications can be achieved by maximizing both parallelism and pipelining. In this paper, the CORDIC based hardware primitives of 3-D rotation with high throughput 3-D vector interpolation are presented. The proposed architecture for 3-D vector interpolator, which is based on the redundant CORDIC arithmetic, has been implemented by VLSI.
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Proceedings
9th Joint International Conference on Information Sciences (JCIS-06)
Part of series
Advances in Intelligent Systems Research
Publication Date
October 2006
ISBN
978-90-78677-01-7
ISSN
1951-6851
DOI
https://doi.org/10.2991/jcis.2006.232How to use a DOI?
Open Access
This is an open access article distributed under the CC BY-NC license.

Cite this article

TY  - CONF
AU  - Tze-Yun Sung
PY  - 2006/10
DA  - 2006/10
TI  - An Efficient CORDIC-Based Vector Interpolator in Power-Aware 3-D Graphics Rendering
BT  - 9th Joint International Conference on Information Sciences (JCIS-06)
PB  - Atlantis Press
SP  - 360
EP  - 363
SN  - 1951-6851
UR  - https://doi.org/10.2991/jcis.2006.232
DO  - https://doi.org/10.2991/jcis.2006.232
ID  - Sung2006/10
ER  -