Warpage Reduction for Integrated Circuit in an Electronics Manufacturing Plant

DOI

10.2991/itms-15.2015.110How to use a DOI?

Keywords

Integrated circuit; Warpage; Six Sigma

Abstract

The purpose of this research is to reduce the defect parts per million (DPPM) of the thickness out of specification caused by module warpage. Six Sigma approach was applied and the 2k full factorial design with three replicates at 95% confident level was used to determine the significant factors to the module warpage. The significant factors comprised dam temperature, fill temperature and curing temperature. Box-Behnken design was also used to optimize the level of the significant factors. The results suggest that the encapsulation machine dam temperature, fill temperature and the curing temperature should be set at 30°C, 65°C and 41°C, respectively. The confirmed runs show that DPPM of the thickness out of specification is reduced from 600 to 184.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - S. Pisutkulakij
AU  - P. Chutima
PY  - 2015/11
DA  - 2015/11
TI  - Warpage Reduction for Integrated Circuit in an Electronics Manufacturing Plant
BT  - Proceedings of the 2015 International Conference on Industrial Technology and Management Science
PB  - Atlantis Press
SP  - 458
EP  - 461
SN  - 2352-538X
UR  - https://doi.org/10.2991/itms-15.2015.110
DO  - 10.2991/itms-15.2015.110
ID  - Pisutkulakij2015/11
ER  -