FPGA Implementation of AES-256 Integrated with Block chain Framework for High-Security Data Applications

DOI

10.2991/978-94-6239-697-5_24How to use a DOI?

Keywords

AES-256; FPGA; VHDL; Block chain Integration; SHA-256; Cryptography Hardware; High-Security Data; IoT Security; Hardware Acceleration

Abstract

In a world increasingly under siege from would-be cyber saboteurs, the safe storage of very high value data means not only powerful encryption but also fool-proof ways to ensure that its integrity has remained uncompromised. In this article, we describe a lightweight block chain framework with FPGA implementation of AES-256 and its targeted applications on security demanding but resource-limited environments such as IoT devices or edge computing. This design uses the parallel processing capability of FPGA to realize a real-time throughput greater than 10 Gbps and assures that latency is minimized to less than 50 ns per block. Some of the key innovations include a hardware-accelerated Merkle tree for block chain consensus, and dynamic key scheduling itself to counter side-channel attacks. Synthesis on Xilinx Virtex-7 FPGA: 92% LUT utilization (power footprint of 1.2 W) in speed is speeds up toof over15x faster than complete software solutions Empirical results confirm improved brute-force and fault-injection resilience, demonstrating that this hybrid approach is a practical secure data pipeline for block chain in finance, health care and autonomous systems.

Copyright

© 2026 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - Vibhuti Dhakre
AU  - Aditya Mandloi
PY  - 2026
DA  - 2026/06/04
TI  - FPGA Implementation of AES-256 Integrated with Block chain Framework for High-Security Data Applications
BT  - Proceedings of the Conference on Bridging Engineering Disciplines with AI and Machine Learning (BEDAIML 2026)
PB  - Atlantis Press
SP  - 280
EP  - 295
SN  - 1951-6851
UR  - https://doi.org/10.2991/978-94-6239-697-5_24
DO  - 10.2991/978-94-6239-697-5_24
ID  - Dhakre2026
ER  -