Design of Double-Precision Floating-Point Division and Square Root Based on SRT Algorithm
- 10.2991/ccit-14.2014.92How to use a DOI?
- SRT4, floating-point division and square root, on-the-fly conversion
In the process of scientific computing, digital signals processing, communication and image processing, division and square root are the widely used basic operation. This article designs a unit of floating-point division and square root based on SRT4 algorithm. It reduces the iterative division and square root calculation delay by using parallel processing of quotient and residue addition and the on-the-fly conversion technology. At the same time, it reduces hardware resources and saves area by adopting reuse the lookup table and the adder. Experiments show that the cell area is 9812.3087um2, the power is 10.7854mW, the cycles per division instruction is 31, the cycles per square root instruction is 28, comprehensive frequency up to 2.5GHz with 40nm technology library and the timing constraint 400ps.
- © 2014, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Jiyang Chen AU - Yuanxi Peng AU - Yuanwu Lei AU - Ziye Deng PY - 2014/01 DA - 2014/01 TI - Design of Double-Precision Floating-Point Division and Square Root Based on SRT Algorithm BT - Proceedings of the 2014 International Conference on Computer, Communications and Information Technology PB - Atlantis Press SP - 355 EP - 361 SN - 1951-6851 UR - https://doi.org/10.2991/ccit-14.2014.92 DO - 10.2991/ccit-14.2014.92 ID - Chen2014/01 ER -