Design and Implementation of an Improved Costas Loop Circuits by Using FPGA
Fangcheng Xing, Suzhen Wang, Weihua Zong, Shujian Zhang
Available Online August 2016.
- https://doi.org/10.2991/cset-16.2016.47How to use a DOI?
- Improved structure of the Costas loop, FPGA, FIR filter, Multiplier
- With the advantages of high integration, high reliability, fast processing speed and online programming, the field-programmable gate array (FPGA) has become a hotspot of the studies on digital communication systems. In a suppressed carrier digital communication system, the quality of carrier extraction has a profound effect on demodulation performance. The traditional analog Costas loop performs poorly due to the imbalance between In-phase branch and Quadrature branch and the limit of analog circuit such as zero drift. Adopting digital circuit designed by FPGA can balance both In-phase and Quadrature branch, avoid these problems effectively. The realization of traditional Costas loop occupies large resources of FPGA. This paper improves the traditional structure of Costas loop according to the characteristics of FPGA devices, introduces an improved structure of the Costas loop which reduces the number of multipliers and adders and improves operation speed and reliability.
- Open Access
- This is an open access article distributed under the CC BY-NC license.
Cite this article
TY - CONF AU - Fangcheng Xing AU - Suzhen Wang AU - Weihua Zong AU - Shujian Zhang PY - 2016/08 DA - 2016/08 TI - Design and Implementation of an Improved Costas Loop Circuits by Using FPGA BT - 2016 International Conference on Computer Science and Electronic Technology PB - Atlantis Press SP - 201 EP - 204 SN - 2352-538X UR - https://doi.org/10.2991/cset-16.2016.47 DO - https://doi.org/10.2991/cset-16.2016.47 ID - Xing2016/08 ER -