Proceedings of the 2016 International Conference on Computer Science and Electronic Technology

Design and Implementation of an Improved Costas Loop Circuits by Using FPGA

Authors
Fangcheng Xing, Suzhen Wang, Weihua Zong, Shujian Zhang
Corresponding Author
Fangcheng Xing
Available Online August 2016.
DOI
https://doi.org/10.2991/cset-16.2016.47How to use a DOI?
Keywords
Improved structure of the Costas loop, FPGA, FIR filter, Multiplier
Abstract
With the advantages of high integration, high reliability, fast processing speed and online programming, the field-programmable gate array (FPGA) has become a hotspot of the studies on digital communication systems. In a suppressed carrier digital communication system, the quality of carrier extraction has a profound effect on demodulation performance. The traditional analog Costas loop performs poorly due to the imbalance between In-phase branch and Quadrature branch and the limit of analog circuit such as zero drift. Adopting digital circuit designed by FPGA can balance both In-phase and Quadrature branch, avoid these problems effectively. The realization of traditional Costas loop occupies large resources of FPGA. This paper improves the traditional structure of Costas loop according to the characteristics of FPGA devices, introduces an improved structure of the Costas loop which reduces the number of multipliers and adders and improves operation speed and reliability.
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This is an open access article distributed under the CC BY-NC license.

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Proceedings
2016 International Conference on Computer Science and Electronic Technology
Part of series
Advances in Computer Science Research
Publication Date
August 2016
ISBN
978-94-6252-213-8
ISSN
2352-538X
DOI
https://doi.org/10.2991/cset-16.2016.47How to use a DOI?
Open Access
This is an open access article distributed under the CC BY-NC license.

Cite this article

TY  - CONF
AU  - Fangcheng Xing
AU  - Suzhen Wang
AU  - Weihua Zong
AU  - Shujian Zhang
PY  - 2016/08
DA  - 2016/08
TI  - Design and Implementation of an Improved Costas Loop Circuits by Using FPGA
BT  - 2016 International Conference on Computer Science and Electronic Technology
PB  - Atlantis Press
SP  - 201
EP  - 204
SN  - 2352-538X
UR  - https://doi.org/10.2991/cset-16.2016.47
DO  - https://doi.org/10.2991/cset-16.2016.47
ID  - Xing2016/08
ER  -