VeriNP: A FPGA-Based Verification Platform for General-Purpose Many-Core Network Processors

DOI

10.2991/csic-15.2015.86How to use a DOI?

Keywords

General-purpose many-core, Network processor, Verification platform, Packet scheduling algorithm, FPGA

Abstract

General-purpose many-core network processors have been widely used in network packet processing due to its high programmabilityandparallel processing ability.The design of general-purpose many-core network processorsinvolvesa lotof key technologies, including packet scheduling, inter-core communication, co-processing,etc.The verification of these technologies is essential before applied to the system. However, there are some of limitations in the current software-based verification platform, such as low simulation speed and fidelity. A FPGA-based verification platform for general-purpose many-core network processors (VeriNP) is proposed in this paper. The VeriNPsupportsverification of network processor for at least 16 real RISC CPU cores, and the frequent of cores can run at 100MHz or higher. Based on the VeriNP platform, two packet scheduling algorithms are studied and verified.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Jinfeng Huang
AU  - Hongbin Wu
AU  - Tao Li
AU  - Hui Yang
AU  - Zhigang Sun
PY  - 2015/07
DA  - 2015/07
TI  - VeriNP: A FPGA-Based Verification Platform for General-Purpose Many-Core Network Processors
BT  - Proceedings of the 2015 International Conference on Computer Science and Intelligent Communication
PB  - Atlantis Press
SP  - 361
EP  - 364
SN  - 2352-538X
UR  - https://doi.org/10.2991/csic-15.2015.86
DO  - 10.2991/csic-15.2015.86
ID  - Huang2015/07
ER  -