Realization of High-Performance Confidential Data Transmission Based on FPGA
- 10.2991/csss-14.2014.133How to use a DOI?
- AES, FPGA, hardware encryption
This paper uses advanced encryption standard, AES, to implement encryption algorithm and FPGA devices to achieve hardware encryption. AES commonly used to provide several security services such as data confidentiality. However, it is a challenge to design efficient hardware architectures with small hardware resource usage. The system is implemented in hardware environment using Verilog HDL. The method has the advantage of full hardware circuitry and can update its own cryptographic algorithm module. Hardware encryption system is based on cryptographic devices and appropriate software program. FPGA can modify the hardware programming repeatedly, its flexibility and scalability make it enable to meet this demand in the encryption field, and reduce costs and improve security. The logic circuit module of cryptographic algorithm has a high flexibility in design, because users can define a specific structure of the cipher algorithm module.
- © 2014, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Fan Yu AU - Peipei Yang PY - 2014/06 DA - 2014/06 TI - Realization of High-Performance Confidential Data Transmission Based on FPGA BT - Proceedings of the 3rd International Conference on Computer Science and Service System PB - Atlantis Press SP - 569 EP - 572 SN - 1951-6851 UR - https://doi.org/10.2991/csss-14.2014.133 DO - 10.2991/csss-14.2014.133 ID - Yu2014/06 ER -