Optimization of Slice and Power-Efficient MUX-Based Adder Design for High Performance Computing Architectures

DOI

10.2991/978-94-6239-616-6_75How to use a DOI?

Keywords

Modified Carry Lookahead Adder (MCLA); Ripple Carry Adder (RCA); FPGA; Hardware Description Language (HDL) code; Logic Style

Abstract

Design procedures significantly influence a device’s timing performance, logic usage, and system consistency when developing complicated system designs. For programmable logic designs, the quality of results is greatly impacted by the coding styles used in the HDL. Synthesis tools maximize the performance and logic use of the HDL code, but they cannot understand the design’s intention. The reliability of the design, timing performance, and logic consumption can all be impacted by design style. This research presents a new adder design that utilizes a single XOR gate, reducing the gate density and circuit complexity compared to its existing counterpart. The proposed adder experimentation is performed on Altera Cyclone II (Family), EP2C70F896C7 (Device) is manufactured using TSMC 90nm Process with a 3-metal layer CMOS process. All the simulation processes are carried out in the same environment by fixing the input voltage of 0 to 1.2V. The intrigues of investigation are combinational propagation delay tpd, slice utilized LE, and thermal static and dynamic power. This research presents that the proposed adder topology synthesis outperforms the existing adder structure to a great extent. The proposed adder structure is incorporated in Carry Lookahead Adder (CLA), Ripple Carry Adder (RCA), and Bypass Adder (ByA). From the simulation, it is analyzed that the proposed structure has a maximum improvement of 52% in delay and 36% improvement in power dissipation, when compared to the existing carry lookahead adder structure.

Copyright

© 2026 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

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TY  - CONF
AU  - B. Pradeepa
AU  - A. V. Ananthalakshmi
PY  - 2026
DA  - 2026/03/31
TI  - Optimization of Slice and Power-Efficient MUX-Based Adder Design for High Performance Computing Architectures
BT  - Proceedings of the International Conference on Artificial Intelligence and Secure Data Analytics (ICAISDA 2025)
PB  - Atlantis Press
SP  - 1023
EP  - 1036
SN  - 1951-6851
UR  - https://doi.org/10.2991/978-94-6239-616-6_75
DO  - 10.2991/978-94-6239-616-6_75
ID  - Pradeepa2026
ER  -