Design of FPGA Hardware based on Genetic Algorithm

DOI

10.2991/iccia-19.2019.15How to use a DOI?

Keywords

FPGA; Genetic algorithm; Parallelism; Pipeline structure.

Abstract

In order to improve the running speed of hardware and the utilization rate of resources, firstly, this paper use genetic algorithm to realize serial and pipeline hardware implementation. Then, the genetic algorithm is improved on the implementation method. In the process of improvement, the pipeline is introduced into the parallel mechanism. Finally, the TSP problem and function extreme value problem are used to verify the resource consumption and running speed of FPGA respectively. The experimental results in this paper show that the two schemes are less expensive in terms of hardware implementation, less expensive in operation and high in efficiency, and the algorithm can also be widely used in the occasions with higher applicability.

Copyright

© 2019, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Xinxin Sun
AU  - Juan Li
AU  - Fenxian Tian
AU  - Yanshuang Chen
AU  - Jun Yang
PY  - 2019/07
DA  - 2019/07
TI  - Design of FPGA Hardware based on Genetic Algorithm
BT  - Proceedings of the 3rd International Conference on Computer Engineering, Information Science & Application Technology (ICCIA 2019)
PB  - Atlantis Press
SP  - 102
EP  - 108
SN  - 2352-538X
UR  - https://doi.org/10.2991/iccia-19.2019.15
DO  - 10.2991/iccia-19.2019.15
ID  - Sun2019/07
ER  -