A Novel Descriptor-based Output Scheduling Technique forGeneral Multi-Core Network Processor

DOI

10.2991/iccnce.2013.161How to use a DOI?

Keywords

network processor, output scheduling, packet descriptor.

Abstract

Output scheduling is an important QoS technique for the network processor. The packet-based output scheduling technique is widely used in general multi-core network processor design due to its simplicity. However, large on-chip packet buffer required by the technique increases the chip area and production cost. Aiming at the problem, a novel output scheduling technique based on packet descriptor is proposed in this paper. The descriptor-based output scheduling technique can reduce storage space requirements without decreasing of system performance. Moreover, it can reduce the output latency of the packet traversing the network processor. Theoretical analysis shows that the proposed descriptor-based output scheduling technique has lower storage requirement compared with the packet-based output scheduling technique. The experiments based on FPGA prove the feasibility of the technique.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - YongTing Hu
AU  - YanLong Zhang
AU  - Tao Li
AU  - ZhiGang Sun
PY  - 2013/07
DA  - 2013/07
TI  - A Novel Descriptor-based Output Scheduling Technique forGeneral Multi-Core Network Processor
BT  - Proceedings of the International Conference on Computer, Networks and Communication Engineering (ICCNCE 2013)
PB  - Atlantis Press
SP  - 650
EP  - 653
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccnce.2013.161
DO  - 10.2991/iccnce.2013.161
ID  - Hu2013/07
ER  -