Improved Node Matrix Optimization Method of Test Points at Circuit Board
- 10.2991/iccset-14.2015.109How to use a DOI?
- circuit board, fault diagnosis, detection, optimization method
Graph theory is applied in this paper to optimization design of test point set in circuit board fault diagnosis. The optimal detection node set of a circuit board can be established by a improved node matrix. The improved node matrix can also regenerate topology network graph of a circuit, which reflects the relationship among every node and the working status of all components in the circuit.
- © 2015, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Feng-yu Li AU - Yu-kun Yan AU - Long-fe Zhang AU - Zhi Chen AU - Long-tao Liao AU - Kai Xiao PY - 2015/01 DA - 2015/01 TI - Improved Node Matrix Optimization Method of Test Points at Circuit Board BT - Proceedings of the 2014 International Conference on Computer Science and Electronic Technology PB - Atlantis Press SP - 494 EP - 497 SN - 2352-538X UR - https://doi.org/10.2991/iccset-14.2015.109 DO - 10.2991/iccset-14.2015.109 ID - Li2015/01 ER -