AVS 3D Real-time Decoder Design and Implementation Based on FPGA/SoC Platform

DOI

10.2991/icismme-15.2015.344How to use a DOI?

Keywords

3D video; stereo-packing algorithm; decoder design; FPGA/SoC Co-platform

Abstract

AVS(audio video coding standard)Group formulates stereo-packing scheme aimed at 3D video. In this paper, based on stereo-packing algorithm, using FPGA hardware accelerate module to parse the stereo-packing ES stream syntax element and cooperating with the Xilinx ZYNQ 7020 SoC development board ,we complete the AVS 3D decoder on FPGA/SoC Co-platform. Using HDMI port to export the decoded data to the 3D display device, we get the 3D video with depth information and verify the validity of AVS 3D real-time decoder.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Peng-fei Ren
AU  - Hong-yang Yu
PY  - 2015/07
DA  - 2015/07
TI  - AVS 3D Real-time Decoder Design and Implementation Based on FPGA/SoC Platform
BT  - Proceedings of the First International Conference on Information Sciences, Machinery, Materials and Energy
PB  - Atlantis Press
SP  - 1660
EP  - 1666
SN  - 1951-6851
UR  - https://doi.org/10.2991/icismme-15.2015.344
DO  - 10.2991/icismme-15.2015.344
ID  - Ren2015/07
ER  -