Smart-Eyes: a FPGA-based smart camera platform with efficient multi-port memory controller
Xie Kunzhi, Qiao Fei, Qi Wei, Yang Huazhong
Available Online November 2013.
- https://doi.org/10.2991/icmt-13.2013.200How to use a DOI?
- Smart Camera; FPGA; Multi-Port Memory Controller; memory mapping; prefetching mechanism
- In this paper, a FPGA-based smart camera platform is proposed. A Xilinx FPGA has been adopted as the core device. Xilinx ISE Design Suite has been used as the design tool and Verilog as the program language. In order to validate the platform, two real-time demonstrations have been implemented. In order to achieve a better tradeoff between performance and power consumption, a novel Multi-Port Memory Controller (MPMC) has been proposed. With a new memory mapping method and prefetching mechanism, the proposed MPMC outperforms Xilinx’s MPMC (at least 25% optimization) in terms of data access. Additionally, the utilization of hardware resources of the FPGA is less than 5%. Thus the proposed Smart-Eyes can be further adopted in many reasonable real-time algorithms and applications.
- Open Access
- This is an open access article distributed under the CC BY-NC license.
Cite this article
TY - CONF AU - Xie Kunzhi AU - Qiao Fei AU - Qi Wei AU - Yang Huazhong PY - 2013/11 DA - 2013/11 TI - Smart-Eyes: a FPGA-based smart camera platform with efficient multi-port memory controller BT - 3rd International Conference on Multimedia Technology(ICMT-13) PB - Atlantis Press SN - 1951-6851 UR - https://doi.org/10.2991/icmt-13.2013.200 DO - https://doi.org/10.2991/icmt-13.2013.200 ID - Kunzhi2013/11 ER -