Design for realizing arbitrary fractional divider based on FPGA which duty cycle is up to 50%

DOI

10.2991/isccca.2013.15How to use a DOI?

Keywords

fractional divider, FPGA, duty cycle

Abstract

This paper proposes a novel method for realizing arbitrary fractional divider based on FPGA. Analyzing the limitations of the existing frequency-divided methods, a new model which consists of two-level dividers is put forward. An arbitrary frequency-divided clock output can be obtained by this method approaching 50% of duty cycle. When the division factor is greater than 128, the duty cycle can be very close to 50% of the clock output. This method is proved to be feasible on the FPGA chip of ALTERA.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Songwei Zhang
AU  - Cheng Zhao
PY  - 2013/02
DA  - 2013/02
TI  - Design for realizing arbitrary fractional divider based on FPGA which duty cycle is up to 50%
BT  - Proceedings of the 2nd International Symposium on Computer, Communication, Control and Automation (ISCCCA 2013)
PB  - Atlantis Press
SP  - 58
EP  - 61
SN  - 1951-6851
UR  - https://doi.org/10.2991/isccca.2013.15
DO  - 10.2991/isccca.2013.15
ID  - Zhang2013/02
ER  -