FPGA Implementation of Rate Control for JPEG2000

DOI

10.2991/jimet-15.2015.42How to use a DOI?

Keywords

JPEG2000, Rate control, Tier1 coding, Rate distortion estimation, FPGA.

Abstract

This paper presents a FPGA implementation of rate control system for JPEG2000. The input image is discrete wavelet transformed, and the wavelet coefficients are encoded by Tier1 coding with rate distortion estimation. During the process of the Tier1 coding, the bit rate for each code block is allocated and the bit stream is then truncated to produce the final bit stream. The Verilog HDL modules for the rate control system are designed, simulated and synthesized to Altera’s FPGA. The result shows that the architecture proposed in this paper is correct.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Shijie Qiao
AU  - Aiqing Yi
AU  - Yuan Yang
PY  - 2015/12
DA  - 2015/12
TI  - FPGA Implementation of Rate Control for JPEG2000
BT  - Proceedings of the 2015 Joint International Mechanical, Electronic and Information Technology Conference
PB  - Atlantis Press
SP  - 230
EP  - 234
SN  - 2352-538X
UR  - https://doi.org/10.2991/jimet-15.2015.42
DO  - 10.2991/jimet-15.2015.42
ID  - Qiao2015/12
ER  -