Low-Voltage Low-Power Pipelined Input Subsampled Replica Algorithmic Noise-Tolerant Motion Estimation Circuit Design

DOI

10.2991/3ca-13.2013.6How to use a DOI?

Keywords

low voltage; low power; pipeline; algorithmic noise-tolerant; motion estimation

Abstract

In this paper, we proposed a new pipelined ISR-ANT ME design to further shorten the critical path of the ISR-ANT ME circuit [1], which can make it operate in a lower operating voltage. The proposed design is very simple, which only needs to insert the pipelined register to cut the critical path of ISR-ANT ME into two sections. The PSNR performance can be maintained and the lowest supply voltage can be lowered to 1.2V in the proposed design.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - I-Chyn Wey
AU  - Zhe-Yu Lin
AU  - Yu-Jie Tian
AU  - Sheng-Hong Yu
AU  - Pin-Si Lin
PY  - 2013/04
DA  - 2013/04
TI  - Low-Voltage Low-Power Pipelined Input Subsampled Replica Algorithmic Noise-Tolerant Motion Estimation Circuit Design
BT  - Proceedings of the 2nd International Symposium on Computer, Communication, Control and Automation
PB  - Atlantis Press
SP  - 22
EP  - 25
SN  - 1951-6851
UR  - https://doi.org/10.2991/3ca-13.2013.6
DO  - 10.2991/3ca-13.2013.6
ID  - Wey2013/04
ER  -