Real-time Multi-channel Vision Processing Based on DSP&FPGA
Yu-Bin Zhou, Yu-Ning Yang
Available Online December 2013.
- https://doi.org/10.2991/wiet-13.2013.38How to use a DOI?
- FPGA; DSP; Stereo vision; Image processing.
- In order to realize digital image sequence processing for multi-channel vision in real-time simultaneously, a hardware system with FPGA&DSP is designed. In the system, two ZBT SRAM chips are used as the input and output cache for high data transferring. A FPGA chip is responsible for the core logic controlling and multi-channel video synchronous. Digital videos are sent to the processing module by Camlink bus. Data are exchanged by EMIF and McBSP between FPGA and DSPs. EDMA is used for data transferring between SRAM in FPGA and ZBT SRAM. The QDMA is used for 2D data transferring to 1D into DSP cache. Tasks are assigned to chips by C/OS on master DSP. All this together, real-time data sampling and processing for multi-channel vision was realized.
- Open Access
- This is an open access article distributed under the CC BY-NC license.
Cite this article
TY - CONF AU - Yu-Bin Zhou AU - Yu-Ning Yang PY - 2013/12 DA - 2013/12 TI - Real-time Multi-channel Vision Processing Based on DSP&FPGA BT - AASRI Winter International Conference on Engineering and Technology (AASRI-WIET 2013) PB - Atlantis Press SN - 1951-6851 UR - https://doi.org/10.2991/wiet-13.2013.38 DO - https://doi.org/10.2991/wiet-13.2013.38 ID - Zhou2013/12 ER -