A Precise Model of TSV Parasitic Capacitance Considering Temperature for 3D IC
Quan Deng, Min-Xuan Zhang, Zhen-Yu Zhao, Peng Li
Available Online April 2015.
- https://doi.org/10.2991/amcce-15.2015.306How to use a DOI?
- 3D IC; TSV; Corner; Temperature and Parasitic Capacitance
- As the technology of three dimension integrated circuit (3D IC) develop quickly, through silicon via (TSV) plays a basic and important role. In consideration of real working environment, factors as temperature and working voltage are studied by TCAD simulator. And the contribution of physical sizes and the concentration of doping in the course are analyzed. A new analysis model of capacitance for TSV is given, which is with an error less than 4% with the measurement data. In the range of 25 to 125 degree centigrade with different physical sizes of TSV, this model of TSV’s parasitic capacitance shows a better accuracy and takes less time than the former one. The neglect of temperature in course of design will lead to a big problem in real chip, an accurate mode considering temperature is important both in design and SI analysis.
- Open Access
- This is an open access article distributed under the CC BY-NC license.
Cite this article
TY - CONF AU - Quan Deng AU - Min-Xuan Zhang AU - Zhen-Yu Zhao AU - Peng Li PY - 2015/04 DA - 2015/04 TI - A Precise Model of TSV Parasitic Capacitance Considering Temperature for 3D IC PB - Atlantis Press SN - 1951-6851 UR - https://doi.org/10.2991/amcce-15.2015.306 DO - https://doi.org/10.2991/amcce-15.2015.306 ID - Deng2015/04 ER -