Noise Margin and Delay Analysis of Half Stacked and Full Stacked SRAM Cell Design
- Abstract
In this paper we propose a half stacked and full stacked SRAM cell design for low power application. This based on the “Stacking Effect of Transistors” with stacking of the driver and the load transistors to reduce the total power consumed in the SRAM cell. The results obtained on basis of proposed half stack and full stack SRAM cell are compared and contrasted with the conventional SRAM cell with sleep transistor and normal mode transistor. The proposed full stack cell gives a 30% power reduction in the standby mode. In addition to these, the proposed cell has a superior Static Noise Margin (SNM) of 380mV at a supply voltage of 1.1V. The significant improvements in the results obtained validate our approach for the proposed stacked SRAM cell design for low power memories design.
- Copyright
- © 2013, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Balwinder Raj PY - 2013/04 DA - 2013/04 TI - Noise Margin and Delay Analysis of Half Stacked and Full Stacked SRAM Cell Design BT - Proceedings of the Conference on Advances in Communication and Control Systems (CAC2S 2013) PB - Atlantis Press SP - 14 EP - 17 SN - 1951-6851 UR - https://www.atlantis-press.com/article/6270 ID - Raj2013/04 ER -