Proceedings of the Conference on Advances in Communication and Control Systems-2013

Noise Margin and Delay Analysis of Half Stacked and Full Stacked SRAM Cell Design

Authors
Balwinder Raj
Corresponding Author
Balwinder Raj
Available Online April 2013.
Abstract
In this paper we propose a half stacked and full stacked SRAM cell design for low power application. This based on the “Stacking Effect of Transistors” with stacking of the driver and the load transistors to reduce the total power consumed in the SRAM cell. The results obtained on basis of proposed half stack and full stack SRAM cell are compared and contrasted with the conventional SRAM cell with sleep transistor and normal mode transistor. The proposed full stack cell gives a 30% power reduction in the standby mode. In addition to these, the proposed cell has a superior Static Noise Margin (SNM) of 380mV at a supply voltage of 1.1V. The significant improvements in the results obtained validate our approach for the proposed stacked SRAM cell design for low power memories design.
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Proceedings
Proceedings of the Conference on Advances in Communication and Control Systems-2013
Part of series
Advances in Intelligent Systems Research
Publication Date
April 2013
ISBN
978-90-78677-66-6
Open Access
This is an open access article distributed under the CC BY-NC license.

Cite this article

TY  - CONF
AU  - Balwinder Raj
PY  - 2013/04
DA  - 2013/04
TI  - Noise Margin and Delay Analysis of Half Stacked and Full Stacked SRAM Cell Design
BT  - Proceedings of the Conference on Advances in Communication and Control Systems-2013
PB  - Atlantis Press
UR  - https://www.atlantis-press.com/article/6270
ID  - Raj2013/04
ER  -