Proceedings of the Conference on Advances in Communication and Control Systems-2013

An Optimized Sample Rate Converter for a software radio receiver on FPGA

Authors
Ashok Agarwal, B. Lakshmi
Corresponding Author
Ashok Agarwal
Available Online April 2013.
Abstract
Abstract-Sample Rate Conversion(SRC) and channelization are the two necessary tasks to be implemented for the design of a radio receiver. For a multi-standard software radio with a very high intermediate frequency(IF), which is of the order of 80MHz and above, the implementation of a sample rate converter is highly computationally intensive. In a multi-standard radio receiver the phenomenon of bandpass sampling over samples the required channel with high over sampling ratios(OSR). In this paper we present an optimized implementation of SRC suitable for down conversion of various wireless standards ranging from wireless LAN WiMAX 802.16 to GSM900 system by the method of factorization. A mixer is designed using CORDIC algorithm in the IF stage and a decimator incorporates Cascaded Integrated Comb(CIC) lter as a component for sample rate conversion. We have optimized the CIC lter by reducing the number of bits in CIC lters from one stage to another. Comparison of the hardware resource utilization of this architecture with non-optimized CIC lter reported more than twenty percent reduction in hardware.
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Proceedings
Proceedings of the Conference on Advances in Communication and Control Systems-2013
Part of series
Advances in Intelligent Systems Research
Publication Date
April 2013
ISBN
978-90-78677-66-6
Open Access
This is an open access article distributed under the CC BY-NC license.

Cite this article

TY  - CONF
AU  - Ashok Agarwal
AU  - B. Lakshmi
PY  - 2013/04
DA  - 2013/04
TI  - An Optimized Sample Rate Converter for a software radio receiver on FPGA
BT  - Proceedings of the Conference on Advances in Communication and Control Systems-2013
PB  - Atlantis Press
UR  - https://www.atlantis-press.com/article/6288
ID  - Agarwal2013/04
ER  -