Dynamic Partial Reconfiguration for Discrete Cosine Transform Computation

Abstract

Discrete Cosine Transform is one of the most important building blocks for the emerging video coding standard, H.264. In this paper, architecture for DCT computation, a hardware intensive operation, using dynamic partial reconfiguration is proposed. Field programmable gate array (FPGA), due to inherent parallelism, is obvious choice for the task. The architecture can perform DCT computations for different zones and change the configuration of processing elements. The unused elements can be used for other processing Moreover the functions being performed on the parts of the FPGA that are not being reconfigured will not be interrupted during reconfiguration.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Bhavesh Jaiswal
AU  - Nagendra Gajjar
PY  - 2013/04
DA  - 2013/04
TI  - Dynamic Partial Reconfiguration for Discrete Cosine Transform Computation
BT  - Proceedings of the Conference on Advances in Communication and Control Systems (CAC2S 2013)
PB  - Atlantis Press
SP  - 160
EP  - 164
SN  - 1951-6851
UR  - https://www.atlantis-press.com/article/6297
ID  - Jaiswal2013/04
ER  -