Proceedings of the Conference on Advances in Communication and Control Systems-2013

Dynamic Partial Reconfiguration for Discrete Cosine Transform Computation

Authors
Bhavesh Jaiswal, Nagendra Gajjar
Corresponding Author
Bhavesh Jaiswal
Available Online April 2013.
Abstract
Discrete Cosine Transform is one of the most important building blocks for the emerging video coding standard, H.264. In this paper, architecture for DCT computation, a hardware intensive operation, using dynamic partial reconfiguration is proposed. Field programmable gate array (FPGA), due to inherent parallelism, is obvious choice for the task. The architecture can perform DCT computations for different zones and change the configuration of processing elements. The unused elements can be used for other processing Moreover the functions being performed on the parts of the FPGA that are not being reconfigured will not be interrupted during reconfiguration.
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Proceedings
Proceedings of the Conference on Advances in Communication and Control Systems-2013
Part of series
Advances in Intelligent Systems Research
Publication Date
April 2013
ISBN
978-90-78677-66-6
Open Access
This is an open access article distributed under the CC BY-NC license.

Cite this article

TY  - CONF
AU  - Bhavesh Jaiswal
AU  - Nagendra Gajjar
PY  - 2013/04
DA  - 2013/04
TI  - Dynamic Partial Reconfiguration for Discrete Cosine Transform Computation
BT  - Proceedings of the Conference on Advances in Communication and Control Systems-2013
PB  - Atlantis Press
UR  - https://www.atlantis-press.com/article/6297
ID  - Jaiswal2013/04
ER  -