Real-time Buffering, Parallel Processing and High-Speed Transmission System for Multi-Channel Video Images Based on ADER
- 10.2991/cnci-19.2019.42How to use a DOI?
- Image caching and processing, High-speed trans- mission, Address-Data-Event Representation (ADER), Field programmable gate array (FPGA), brain inspired processing chip.
Aiming at the problem that the brain inspired multi- core processing chip processes high-speed images in real time, a real-time data buffer of multi-channel high-definition images is designed, and the image is processed and transmitted at the pixel level. The design uses field-programmable gate array FPGA as the processing platform, and uses Address-Data-Event Representation (ADER) as a model to receive video stream data in real time, and the advantages of FPGA high-speed parallel processing are preliminary. Compression and grayscale processing are performed to continuously buffer and send and receive data in real time. In the data transmission, in order to adapt the multi-core processing chip parallel computing, the frame of data transmission protocol is customized at the bottom layer to realize continuous buffering, parallel processing and real- time transmission and reception of multi-channel high-definition camera data.
- © 2019, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - MingWang Chen AU - JianPing Xiong AU - Cheng Ma AU - Qi Zhao AU - Sen Feng PY - 2019/05 DA - 2019/05 TI - Real-time Buffering, Parallel Processing and High-Speed Transmission System for Multi-Channel Video Images Based on ADER BT - Proceedings of the 2019 International Conference on Computer, Network, Communication and Information Systems (CNCI 2019) PB - Atlantis Press SP - 282 EP - 289 SN - 2352-538X UR - https://doi.org/10.2991/cnci-19.2019.42 DO - 10.2991/cnci-19.2019.42 ID - Chen2019/05 ER -