Proceedings of the 2017 International Conference on Electronic Industry and Automation (EIA 2017)

An Approach for Checking RTL Design Signal Sources and Destinations

Authors
Jianguo SONG, Aojie CHEN, Tao GUO
Corresponding Author
Jianguo SONG
Available Online July 2017.
DOI
https://doi.org/10.2991/eia-17.2017.48How to use a DOI?
Keywords
System-on-Chip; Verilog HDL; RTL; connectivity; formal check; signal connection; Perl
Abstract

Formal check provides a method for detecting problems of SoC design in early time of verification. Looking at SoC design issues, most of design integration errors come from modules connectivity. Combining above two points, this paper descripts an approach check signal connectivity with formal check method. The approach parses Verilog HDL RTL code through a program, which writes by script language Perl, to analysis signals connectivity. It's helpful for both SoC designer and verification engineer.

Copyright
© 2017, the Authors. Published by Atlantis Press.
Open Access
This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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Volume Title
Proceedings of the 2017 International Conference on Electronic Industry and Automation (EIA 2017)
Series
Advances in Intelligent Systems Research
Publication Date
July 2017
ISBN
10.2991/eia-17.2017.48
ISSN
1951-6851
DOI
https://doi.org/10.2991/eia-17.2017.48How to use a DOI?
Copyright
© 2017, the Authors. Published by Atlantis Press.
Open Access
This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Cite this article

TY  - CONF
AU  - Jianguo SONG
AU  - Aojie CHEN
AU  - Tao GUO
PY  - 2017/07
DA  - 2017/07
TI  - An Approach for Checking RTL Design Signal Sources and Destinations
BT  - Proceedings of the 2017 International Conference on Electronic Industry and Automation (EIA 2017)
PB  - Atlantis Press
SP  - 223
EP  - 226
SN  - 1951-6851
UR  - https://doi.org/10.2991/eia-17.2017.48
DO  - https://doi.org/10.2991/eia-17.2017.48
ID  - SONG2017/07
ER  -