High-speed and High-efficient Modulo (2n-3) Multipliers

DOI

10.2991/emcs-16.2016.500How to use a DOI?

Keywords

Residue number system (RNS); Modulo; Multiplier

Abstract

In this paper, an algorithm for designing efficient modulo 2n-3 multipliers is proposed. With this algorithm, we can design the fastest among all known modulo 2n-3 multipliers by applying some simple correction terms. Implemented using 90nm CMOS process technology the proposed modulo 2n-3 multiplier can improve the current state of the art by 3.9% on the average in terms of area and 10.5-36.4% in terms of performance delay.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Huihua Liu
AU  - Lei Li
AU  - Wanting Zhou
PY  - 2016/01
DA  - 2016/01
TI  - High-speed and High-efficient Modulo (2n-3) Multipliers
BT  - Proceedings of the 2016 International Conference on Education, Management, Computer and Society
PB  - Atlantis Press
SP  - 1991
EP  - 1995
SN  - 2352-538X
UR  - https://doi.org/10.2991/emcs-16.2016.500
DO  - 10.2991/emcs-16.2016.500
ID  - Liu2016/01
ER  -