Realization of High-Performance Confidential Data Transmission Based on FPGA
- https://doi.org/10.2991/emcs-16.2016.509How to use a DOI?
- AES; FPGA; Hardware encryption
This paper uses advanced encryption standard (AES) to implement encryption algorithm and FPGA devices to achieve hardware encryption. AES commonly used to provide several security services such as data confidentiality. However, it is a challenge to design efficient hardware architectures with small hardware resource usage. The system is implemented in hardware environment using Verilog HDL. The method has the advantage of full hardware circuitry and can update its own cryptographic algorithm module. Hardware encryption system is based on cryptographic devices and appropriate software program. FPGA can modify the hardware programming repeatedly. The logic circuit module of cryptographic algorithm has a high flexibility in design, because users can define a specific structure of the cipher algorithm module.
- © 2016, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Fan Yu AU - Wei Chen AU - Zhongsheng Wang PY - 2016/01 DA - 2016/01 TI - Realization of High-Performance Confidential Data Transmission Based on FPGA BT - Proceedings of the 2016 International Conference on Education, Management, Computer and Society PB - Atlantis Press SP - 2028 EP - 2031 SN - 2352-538X UR - https://doi.org/10.2991/emcs-16.2016.509 DO - https://doi.org/10.2991/emcs-16.2016.509 ID - Yu2016/01 ER -