Proceedings of the 6th International Conference on Electronic, Mechanical, Information and Management Society

Design and Realization of Multi-port Register File based on Schematic Diagram

Authors
Lihua Jiang, Cuihua Zuo
Corresponding Author
Lihua Jiang
Available Online April 2016.
DOI
https://doi.org/10.2991/emim-16.2016.132How to use a DOI?
Keywords
Multi-port register file; Schematic; Programmable logic device; FPGA
Abstract
In cpu design, the register file is a necessary device which save the instruction and data. In this paper, we propose a design method for multi-port register file design in the environment of single-cycle CPU system based on the MIPS instruction set and according to the characteristics of multi-port register file, and the Schematic is introduced in order to speed up the development cycle. Furthermore, we discuss the consideration and operational principle of design and realization in detail. The simulation results for the part constructed by FPGA are also presented. In this example which provides the learning and design innovation for other circuit designed.
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This is an open access article distributed under the CC BY-NC license.

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Proceedings
6th International Conference on Electronic, Mechanical, Information and Management Society
Part of series
Advances in Computer Science Research
Publication Date
April 2016
ISBN
978-94-6252-176-6
ISSN
2352-538X
DOI
https://doi.org/10.2991/emim-16.2016.132How to use a DOI?
Open Access
This is an open access article distributed under the CC BY-NC license.

Cite this article

TY  - CONF
AU  - Lihua Jiang
AU  - Cuihua Zuo
PY  - 2016/04
DA  - 2016/04
TI  - Design and Realization of Multi-port Register File based on Schematic Diagram
BT  - 6th International Conference on Electronic, Mechanical, Information and Management Society
PB  - Atlantis Press
SP  - 631
EP  - 636
SN  - 2352-538X
UR  - https://doi.org/10.2991/emim-16.2016.132
DO  - https://doi.org/10.2991/emim-16.2016.132
ID  - Jiang2016/04
ER  -