Proceedings of the 3rd International Conference on Material, Mechanical and Manufacturing Engineering

A CMOS input buffer with linearization technique for high-speed A/D

Authors
Xi Chen, Liang Li, Mingyuan Xu, Xiaofeng Shen
Corresponding Author
Xi Chen
Available Online August 2015.
DOI
https://doi.org/10.2991/ic3me-15.2015.175How to use a DOI?
Keywords
Input Buffer, Linearization Technique, High-speed A/D
Abstract
A CMOS input buffer with linearization technique for high-speed A/D is introduced. The buffer features high-linearity and low-power consumption. The simulation shows that the SFDR of the buffer is up to 107dB at an input clock of 250MHz with an input signal of 10MHz. A 14-bit 250MSPS pipelined A/D converter integrated this buffer improves its distortion by 5-10 dB.
Open Access
This is an open access article distributed under the CC BY-NC license.

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Proceedings
3rd International Conference on Material, Mechanical and Manufacturing Engineering (IC3ME 2015)
Part of series
Advances in Engineering Research
Publication Date
August 2015
ISBN
978-94-6252-100-1
ISSN
2352-5401
DOI
https://doi.org/10.2991/ic3me-15.2015.175How to use a DOI?
Open Access
This is an open access article distributed under the CC BY-NC license.

Cite this article

TY  - CONF
AU  - Xi Chen
AU  - Liang Li
AU  - Mingyuan Xu
AU  - Xiaofeng Shen
PY  - 2015/08
DA  - 2015/08
TI  - A CMOS input buffer with linearization technique for high-speed A/D
BT  - 3rd International Conference on Material, Mechanical and Manufacturing Engineering (IC3ME 2015)
PB  - Atlantis Press
SN  - 2352-5401
UR  - https://doi.org/10.2991/ic3me-15.2015.175
DO  - https://doi.org/10.2991/ic3me-15.2015.175
ID  - Chen2015/08
ER  -