Hot Data Detector based High-Performance NAND and PRAM Hybrid Storage
Yu Zhang, Yi zhi Wu, De min Li, Hai xiao Shan
Available Online August 2013.
- https://doi.org/10.2991/icacsei.2013.37How to use a DOI?
- NAND flash, Phase-changed (PRAM), Hot data detection, Hybrid Storage, Flash Translation Layer.
- The high-performance and low cost NAND Flash and PRAM (Phase-changed RAM) hybrid storage designs have been proposed for embedded systems. However, the system is still suffering from serious performance degradation for continuous write/read operations in the same logical address frequently due to physical constraints of NAND Flash: erase-before-program and different unit size of erase and program operation. To deal with these constraints, a hot data detector is added in the FTL (Flash Translation Layer) of the NAND flash and PRAM hybrid architecture. In this paper, a circular queue based hot data detector algorithm (CQHDD) is proposed, which mainly includes hot-area counting queue design, queue update algorithm and hot-area counting algorithm. Comparing to existing methods, the simulation results show that the read and the write performance of the suggested method improve by 14.2% and 23.7%, respectively, and the average recognition missing rate decreases by 6.3%.
- Open Access
- This is an open access article distributed under the CC BY-NC license.
Cite this article
TY - CONF AU - Yu Zhang AU - Yi zhi Wu AU - De min Li AU - Hai xiao Shan PY - 2013/08 DA - 2013/08 TI - Hot Data Detector based High-Performance NAND and PRAM Hybrid Storage BT - 2013 International Conference on Advanced Computer Science and Electronics Information (ICACSEI 2013) PB - Atlantis Press SN - 1951-6851 UR - https://doi.org/10.2991/icacsei.2013.37 DO - https://doi.org/10.2991/icacsei.2013.37 ID - Zhang2013/08 ER -