Analysis of Various Adder Circuits for Low Power Consumption and Minimum Propagation Delay
- S. Aphale, K. Fakir, S. Kodagali
- Corresponding Author
- S. Aphale
Available Online December 2016.
- https://doi.org/10.2991/iccasp-16.2017.54How to use a DOI?
- Adder, 45nm, D.C analysis, Power-delay-product, Electric tool
- Arithmetic operations are important and most commonly used functions in VLSI applications. 1-single bit full adder digital circuit is the building block that performs the operations such of addition, subtraction, multiplica-tion, etc. Designing, Implementation of single bit full adder circuits in nm submicron process and 45nm deep submicron process are evaluated in this paper. Three adder circuits considered are Conventional adder, Mirror adder and transmission gate logic adder are evaluated in this paper. Schematic and Layout of all three adder circuits in both micron process are administered with D.C and pulse inputs. Evaluation of power-delay product, parasitic capacitance and comparison between performance of adder circuits in both process are asserted. The adders are Modeled using EDA-Electric tool and LT spice simulation software.
- Open Access
- This is an open access article distributed under the CC BY-NC license.
Cite this article
TY - CONF AU - S. Aphale AU - K. Fakir AU - S. Kodagali PY - 2016/12 DA - 2016/12 TI - Analysis of Various Adder Circuits for Low Power Consumption and Minimum Propagation Delay BT - International Conference on Communication and Signal Processing 2016 (ICCASP 2016) PB - Atlantis Press SN - 1951-6851 UR - https://doi.org/10.2991/iccasp-16.2017.54 DO - https://doi.org/10.2991/iccasp-16.2017.54 ID - Aphale2016/12 ER -