A Two-dimensional Analytical Model and Simulation for Dual Material Gate Junctionless Transistor

DOI

10.2991/iccasp-16.2017.56How to use a DOI?

Keywords

Dual Material Gate (DMG); two-dimensional (2-D) modeling; silicon-on-insulator (SOI) MOSFET; Short channel ef-fects (SCEs).

Abstract

To investigate the short channel effect for Dual Material Gate Silicon on Insulator junction-less Transistor (DMG SOI JLT) of a two dimensional channel potential model is developed. This model is validated by simula-tion (COGENDA Visual TCAD) result. It has been observed that for a junction-less transistor with Dual Materi-al Gate (DMG) current driving capability improves secondly, channel potential step function that results drain voltage variation do not affect on barrier between source and channel due to the work function difference of the gate material. This increase in current driving capability increases and hot electron effect, Drain induced barrier lowering problem and reduces its dual material different work function structure.

Copyright

© 2017, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - S. Wagaj
AU  - Y. Chavan
AU  - S. Patil
PY  - 2016/12
DA  - 2016/12
TI  - A Two-dimensional Analytical Model and Simulation for Dual Material Gate Junctionless Transistor
BT  - Proceedings of the International Conference on Communication and Signal Processing 2016 (ICCASP 2016)
PB  - Atlantis Press
SP  - 366
EP  - 373
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccasp-16.2017.56
DO  - 10.2991/iccasp-16.2017.56
ID  - Wagaj2016/12
ER  -