The Design of High Speed Data Acquisition System Based on JESD204B
Yu Wang, Qingzhan Shi, Qi Feng
Available Online July 2016.
- https://doi.org/10.2991/iccia-17.2017.145How to use a DOI?
- Data acquisition system, JESD204B interface, High-speed ADC.
- Recently, various acquisition systems require data converters to provide higher resolution and sampling rates. The physical layout of parallel interfaces and the bit rate limitations of serial LVDS methods pose technical hurdles for designers. The design is based on the classical architecture of FPGA+DSP+ADC of data acquisition system. The High speed ADC is based on JESD204B interface with four slices and two channels, it can meet the requirements of high-speed acquisition, and high-speed sampling of eight channels. It provides a good method for the design and application of various high-speed acquisition systems, and it effectively solves all kinds of problems in parallel transmission of traditional data acquisition, and brings great engineering application value.
- Open Access
- This is an open access article distributed under the CC BY-NC license.
Cite this article
TY - CONF AU - Yu Wang AU - Qingzhan Shi AU - Qi Feng PY - 2016/07 DA - 2016/07 TI - The Design of High Speed Data Acquisition System Based on JESD204B BT - 2nd International Conference on Computer Engineering, Information Science & Application Technology (ICCIA 2017) PB - Atlantis Press SP - 824 EP - 828 SN - 2352-538X UR - https://doi.org/10.2991/iccia-17.2017.145 DO - https://doi.org/10.2991/iccia-17.2017.145 ID - Wang2016/07 ER -