Parallel Random Walk Algorithm in VLSI Analysis

DOI

10.2991/iccsee.2013.178How to use a DOI?

Keywords

parallel computing, random walk, algorithm design

Abstract

Parallel computing techniques were introduced to improve random walk algorithm. A formal model was firstly adopted to explain the random walk problem. And then, the parallel features of random walk algorithm were discussed in detail. Finally, a parallel random walk algorithm was proposed and applied to analyze the VLSI power grid. Experiments were completed at a parallel computing environment of IBM blade computer. Time complexity and the main factors impacting on the execution time of algorithm were analyzed carefully. The experimental results proved that the parallel computing techniques could improve of random walk algorithm effectively. The speedup ratio is close to the maximum value.

Copyright

© 2013, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Jun Guo
AU  - Cangsong Zhang
AU  - Jiao Cui
PY  - 2013/03
DA  - 2013/03
TI  - Parallel Random Walk Algorithm in VLSI Analysis
BT  - Proceedings of the 2nd International Conference on Computer Science and Electronics Engineering (ICCSEE 2013)
PB  - Atlantis Press
SP  - 700
EP  - 703
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccsee.2013.178
DO  - 10.2991/iccsee.2013.178
ID  - Guo2013/03
ER  -