Proceedings of the 2016 4th International Conference on Electrical & Electronics Engineering and Computer Science (ICEEECS 2016)

Research on Cache Coherence Key Technology in Multi-core Processor System

Authors
Su Zhang
Corresponding Author
Su Zhang
Available Online December 2016.
DOI
https://doi.org/10.2991/iceeecs-16.2016.46How to use a DOI?
Keywords
Cache, Coherence Key Technology, Multi-core Processor System
Abstract
The multi-core processor integrates more than one computing core into a single processor and enhances the processor's computing performance through parallel computing of multiple cores. Single-chip multi-processor architecture is the area of concern. This paper briefly discusses the CMP multi-level Cache storage structure, the multi-level structure of the cache caused the consistency problem and the choice of consistency agreement has an important impact on CMP system performance. What kind of Cache consistency model is used and its design scheme are the main contents of this paper.
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This is an open access article distributed under the CC BY-NC license.

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Proceedings
2016 4th International Conference on Electrical & Electronics Engineering and Computer Science (ICEEECS 2016)
Part of series
Advances in Computer Science Research
Publication Date
December 2016
ISBN
978-94-6252-265-7
ISSN
2352-538X
DOI
https://doi.org/10.2991/iceeecs-16.2016.46How to use a DOI?
Open Access
This is an open access article distributed under the CC BY-NC license.

Cite this article

TY  - CONF
AU  - Su Zhang
PY  - 2016/12
DA  - 2016/12
TI  - Research on Cache Coherence Key Technology in Multi-core Processor System
BT  - 2016 4th International Conference on Electrical & Electronics Engineering and Computer Science (ICEEECS 2016)
PB  - Atlantis Press
SN  - 2352-538X
UR  - https://doi.org/10.2991/iceeecs-16.2016.46
DO  - https://doi.org/10.2991/iceeecs-16.2016.46
ID  - Zhang2016/12
ER  -