Proceedings of the 2016 4th International Conference on Electrical & Electronics Engineering and Computer Science (ICEEECS 2016)

The algorithm of thread scheduling with an Improvement Accelerating Critical Section of migration strategy

Authors
Xueming Zhai, Xu Li
Corresponding Author
Xueming Zhai
Available Online December 2016.
DOI
https://doi.org/10.2991/iceeecs-16.2016.109How to use a DOI?
Keywords
Critical Section Migration; Priority Factor; Dynamic Scheduling
Abstract

In multi-core processors,the heterogeneous multi-core processors are more practical than homogeneous multi-core because they have asymmetric cores.Therefore,the multi-thread scheduling among them becomes a hot research topic.In this paper, an Improvement Accelerating Critical Section algorithm is proposed for the improvement of the Accelerating Critical Section algorithm. The algorithm tracks the execution of threads on the cores that contain the critical section and changes the priority factor of threads .It use the priority factor to guide the threads'dynamic migration between the high-performance core and the low-performance cores.The algorithm can accelerate the excution of the critical section and effectively solve the threads block problem on high-performance core that the Accelerating Critical Section causes.This paper use the Simics to simulate heterogeneous multi-core processors system and the inputs are 12 loads with intensive critical sections. The experimental results show that compared to the Accelerating Critical Section algorithm and the Simple Algorithm ,the algorithm this paper proposes has better performance.

Copyright
© 2016, the Authors. Published by Atlantis Press.
Open Access
This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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Volume Title
Proceedings of the 2016 4th International Conference on Electrical & Electronics Engineering and Computer Science (ICEEECS 2016)
Series
Advances in Computer Science Research
Publication Date
December 2016
ISBN
978-94-6252-265-7
ISSN
2352-538X
DOI
https://doi.org/10.2991/iceeecs-16.2016.109How to use a DOI?
Copyright
© 2016, the Authors. Published by Atlantis Press.
Open Access
This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Cite this article

TY  - CONF
AU  - Xueming Zhai
AU  - Xu Li
PY  - 2016/12
DA  - 2016/12
TI  - The algorithm of thread scheduling with an Improvement Accelerating Critical Section of migration strategy
BT  - Proceedings of the 2016 4th International Conference on Electrical & Electronics Engineering and Computer Science (ICEEECS 2016)
PB  - Atlantis Press
SP  - 540
EP  - 545
SN  - 2352-538X
UR  - https://doi.org/10.2991/iceeecs-16.2016.109
DO  - https://doi.org/10.2991/iceeecs-16.2016.109
ID  - Zhai2016/12
ER  -