Proceedings of the 2016 4th International Conference on Machinery, Materials and Information Technology Applications

A 3.75Gbps Configurable Continuous Time Linear Equalizer and 3-tap Decision Feedback Equalizer in 65nm CMOS

Authors
Yong Fu, Zhiping Wen, Lei Chen, Jian Zhang
Corresponding Author
Yong Fu
Available Online January 2017.
DOI
https://doi.org/10.2991/icmmita-16.2016.300How to use a DOI?
Keywords
Rx receiver; Equalizer; Inter-Symbol-Interference(ISI); Continuous Time Linear Equalizer (CTLE); Decision Feedback Equalizer (DFE); Configurable
Abstract
This paper describes the design of the architecture and circuit block of the RX receiver's equalizer, which is used to reduce the inter-symbol-interference(ISI) in high-speed transmission backplane, and a 3,75Gbps configurable Continuous Time Linear Equalizer (CTLE) and 3-tap configurable Decision Feedback Equalizer (DFE) are designed and implemented in 65nm CMOS Technology. Those equalizer can be configured according to different channel conditions and the equalizer provides continuous operation range between 0.5Gbps-3.75Gbps, which are designed to work together to mitigate some or most of hte insertion loss and help the receiver to scale and optimize across different needs and applization. The simulation result shows that the horizontal eye opening of recovered data is 0.75UI at 3.75Gbps and the high frequency boost is up to 11dB.
Open Access
This is an open access article distributed under the CC BY-NC license.

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Cite this article

TY  - CONF
AU  - Yong Fu
AU  - Zhiping Wen
AU  - Lei Chen
AU  - Jian Zhang
PY  - 2017/01
DA  - 2017/01
TI  - A 3.75Gbps Configurable Continuous Time Linear Equalizer and 3-tap Decision Feedback Equalizer in 65nm CMOS
BT  - Proceedings of the 2016 4th International Conference on Machinery, Materials and Information Technology Applications
PB  - Atlantis Press
SP  - 1324
EP  - 1331
SN  - 2352-538X
UR  - https://doi.org/10.2991/icmmita-16.2016.300
DO  - https://doi.org/10.2991/icmmita-16.2016.300
ID  - Fu2017/01
ER  -