Design and Implementation of Parallel LVDS based on RapidIO

DOI

10.2991/isci-15.2015.246How to use a DOI?

Keywords

Parallel LVDS; RapidIO Interconnect; clock-data skew; channel aligner

Abstract

Designed to be compatible with the most popular integrated communications processors, host processors, and networking digital signal processors, RapidIO Interconnect Architecture is a high-performance, packet-switched interconnect technology, where parallel Low-Voltage Differential Signaling (LVDS) is used. This paper first gives a brief introduction on the features of LVDS, and then presents a method to implement the parallel LVDS in the parallel RapidIO protocol using CPLD device and VHDL language; followed by a detailed discussion on the data line transmission errors generated during the process of high-speed data transportation due to the clock-data skew and the difference between transmission lines. A logical component, 4-bit-channel aligner, is developed to solve this sort of transmission errors. Finally a verification circuit board is developed to evaluate the implementation of parallel LVDS data transmission.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

Download article (PDF)

TY  - CONF
AU  - Xiangyang Li
AU  - Rong Li
AU  - Pengfei Zhang
AU  - Jinhua Zhou
PY  - 2015/01
DA  - 2015/01
TI  - Design and Implementation of Parallel LVDS based on RapidIO
BT  - Proceedings of the 2015 International Symposium on Computers & Informatics
PB  - Atlantis Press
SP  - 1867
EP  - 1874
SN  - 2352-538X
UR  - https://doi.org/10.2991/isci-15.2015.246
DO  - 10.2991/isci-15.2015.246
ID  - Li2015/01
ER  -