11th Joint International Conference on Information Sciences

RTL Test Generation via Fault Insertion and Hybrid Satisfiability Solving

Authors
Weimin Wu 0
Corresponding Author
Weimin Wu
0Beijing Jiaotong University
Available Online December 2008.
DOI
https://doi.org/10.2991/jcis.2008.22How to use a DOI?
Keywords
RTL, fault, test generation, satisfiablity.
Abstract
Test generation at RTL (Register-Transfer Level) is a challenging task be-cause bit and word variables co-existent and the high-level functional units impose more complex constraints. We propose an effective way to the problem. In our method, given the circuit as well as the fault point to be checked, we first con-struct a new circuit, miter, by fault inser-tion as well as miter reduction techniques. Then we solve the constraints of the miter by EHSAT, an efficient hybrid satisfiabil-ity solver to obtain the required test vec-tors. Experimental results demonstrate the effectiveness of our method.
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This is an open access article distributed under the CC BY-NC license.

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Proceedings
11th Joint International Conference on Information Sciences
Part of series
Advances in Intelligent Systems Research
Publication Date
December 2008
ISBN
978-90-78677-18-5
ISSN
1951-6851
DOI
https://doi.org/10.2991/jcis.2008.22How to use a DOI?
Open Access
This is an open access article distributed under the CC BY-NC license.

Cite this article

TY  - CONF
AU  - Weimin Wu
PY  - 2008/12
DA  - 2008/12
TI  - RTL Test Generation via Fault Insertion and Hybrid Satisfiability Solving
BT  - 11th Joint International Conference on Information Sciences
PB  - Atlantis Press
SN  - 1951-6851
UR  - https://doi.org/10.2991/jcis.2008.22
DO  - https://doi.org/10.2991/jcis.2008.22
ID  - Wu2008/12
ER  -