RTL Test Generation via Fault Insertion and Hybrid Satisfiability Solving
Weimin Wu 0
0Beijing Jiaotong University
Available Online December 2008.
- https://doi.org/10.2991/jcis.2008.22How to use a DOI?
- RTL, fault, test generation, satisfiablity.
- Test generation at RTL (Register-Transfer Level) is a challenging task be-cause bit and word variables co-existent and the high-level functional units impose more complex constraints. We propose an effective way to the problem. In our method, given the circuit as well as the fault point to be checked, we first con-struct a new circuit, miter, by fault inser-tion as well as miter reduction techniques. Then we solve the constraints of the miter by EHSAT, an efficient hybrid satisfiabil-ity solver to obtain the required test vec-tors. Experimental results demonstrate the effectiveness of our method.
- Open Access
- This is an open access article distributed under the CC BY-NC license.
Cite this article
TY - CONF AU - Weimin Wu PY - 2008/12 DA - 2008/12 TI - RTL Test Generation via Fault Insertion and Hybrid Satisfiability Solving BT - 11th Joint International Conference on Information Sciences PB - Atlantis Press SN - 1951-6851 UR - https://doi.org/10.2991/jcis.2008.22 DO - https://doi.org/10.2991/jcis.2008.22 ID - Wu2008/12 ER -