Application and Implementation of DES Algorithm Based on FPGA

DOI

10.2991/meici-16.2016.149How to use a DOI?

Keywords

Pipeline architecture; FPGA; DES; IP Core

Abstract

In order to meet the data transmission of security and real time requirement in trading system, in this paper, a design scheme of 16 level pipeline encryption system based on FPGA is proposed. Using the 7K325T model of the Xilinx company`s FPGA chip to achieve circuit design. The results show that the circuit can work stably, the maximum frequency of the encryption module is up to 166MHz, and the encryption speed is 10.62Gb/s, which can ensure the security and efficiency of the data.

Copyright

© 2016, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Liuwei Zhao
AU  - Yanbin Zhang
PY  - 2016/09
DA  - 2016/09
TI  - Application and Implementation of DES Algorithm Based on FPGA
BT  - Proceedings of the 2016 6th International Conference on Management, Education, Information and Control (MEICI 2016)
PB  - Atlantis Press
SP  - 715
EP  - 719
SN  - 1951-6851
UR  - https://doi.org/10.2991/meici-16.2016.149
DO  - 10.2991/meici-16.2016.149
ID  - Zhao2016/09
ER  -