An FPGA-based cortical and thalamic silicon neuronal network
- https://doi.org/10.2991/jrnal.2016.2.4.8How to use a DOI?
- silicon neuronal network, neuron model, FPGA, cortex, thalamus.
A DSSN model is a neuron model which is designed to be implemented efficiently by digital arithmetic circuit. In our previous study, we expanded this model to support the neuronal activities of several cortical and thalamic neurons; Regular spiking, fast spiking, intrinsically bursting and low-threshold spike. In this paper, we report our implementation of this expanded DSSN model and a kinetic-model-based silicon synapse on an FPGA device. Here, synaptic efficacy was stored in block RAMs, and external connection was realized based on a bus that conform to the address event representation. We simulated our circuit by the Xilinx Vivado design suit.
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- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - JOUR AU - Takuya Nanami AU - Takashi Kohno PY - 2016 DA - 2016/03/01 TI - An FPGA-based cortical and thalamic silicon neuronal network JO - Journal of Robotics, Networking and Artificial Life SP - 238 EP - 242 VL - 2 IS - 4 SN - 2352-6386 UR - https://doi.org/10.2991/jrnal.2016.2.4.8 DO - https://doi.org/10.2991/jrnal.2016.2.4.8 ID - Nanami2016 ER -