Proceedings of the AASRI Winter International Conference on Engineering and Technology (AASRI-WIET 2013)

Design of a Softdog based on FPGA

Authors
Yulin Zhang, Xinggang Wang
Corresponding Author
Yulin Zhang
Available Online December 2013.
DOI
https://doi.org/10.2991/wiet-13.2013.10How to use a DOI?
Keywords
Softdog; FPGA; AES
Abstract
This paper presents a design of softdog based on FPGA and describes hardware and software design. PC applies the CP2103 to transfers data via the USB to the FPGA device without modifying the application. The SPARTAN XC2S200 FPGA is the core of the softdog. It completes acquiring, processing and sending data. Taking the AES as Encryption algorithm, the design can be working at 255.875MHz using 1520 slices to encrypt data. This method is suitable for the application of the low-cost encryption chip that the data throughput is not critical.
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Proceedings
AASRI Winter International Conference on Engineering and Technology (AASRI-WIET 2013)
Part of series
Advances in Intelligent Systems Research
Publication Date
December 2013
ISBN
978-90786-77-95-6
ISSN
1951-6851
DOI
https://doi.org/10.2991/wiet-13.2013.10How to use a DOI?
Open Access
This is an open access article distributed under the CC BY-NC license.

Cite this article

TY  - CONF
AU  - Yulin Zhang
AU  - Xinggang Wang
PY  - 2013/12
DA  - 2013/12
TI  - Design of a Softdog based on FPGA
BT  - AASRI Winter International Conference on Engineering and Technology (AASRI-WIET 2013)
PB  - Atlantis Press
SN  - 1951-6851
UR  - https://doi.org/10.2991/wiet-13.2013.10
DO  - https://doi.org/10.2991/wiet-13.2013.10
ID  - Zhang2013/12
ER  -