Proceedings of the 2016 International Conference on Advanced Electronic Science and Technology (AEST 2016)

Design and optimization of JFET region for high voltage 4H-SiC IGBT

Authors
Tongtong Yang, Runhua Huang, Song Bai
Corresponding Author
Tongtong Yang
Available Online November 2016.
DOI
https://doi.org/10.2991/aest-16.2016.124How to use a DOI?
Keywords
JFET; 4H-SiC; IGBT.
Abstract
The JFET region is an essential for IGBT devices. This paper mainly uses the Silvaco Atlas simulation tool to investigate the dependence of the characteristics of IGBT on JFET region. The simulations focus on the study of the width and concentration of JFET region at different interface charge densities. The results show that there is a paradox between the optimization of turn-on characteristics and blocking characteristics of IGBT devices. The best combinations of width and concentration at different charge densities are determined in considerations of both the turn-on and blocking characteristics. The simulation results show that a JFET width of 3æm and a doping concentration of 6e15cm-3 are the best combination in most situations for high voltage (>20kV) IGBT devices.
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Proceedings
2016 International Conference on Advanced Electronic Science and Technology (AEST 2016)
Part of series
Advances in Intelligent Systems Research
Publication Date
November 2016
ISBN
978-94-6252-257-2
ISSN
1951-6851
DOI
https://doi.org/10.2991/aest-16.2016.124How to use a DOI?
Open Access
This is an open access article distributed under the CC BY-NC license.

Cite this article

TY  - CONF
AU  - Tongtong Yang
AU  - Runhua Huang
AU  - Song Bai
PY  - 2016/11
DA  - 2016/11
TI  - Design and optimization of JFET region for high voltage 4H-SiC IGBT
BT  - 2016 International Conference on Advanced Electronic Science and Technology (AEST 2016)
PB  - Atlantis Press
SN  - 1951-6851
UR  - https://doi.org/10.2991/aest-16.2016.124
DO  - https://doi.org/10.2991/aest-16.2016.124
ID  - Yang2016/11
ER  -