The Optimization Scheme Of The Leakage Current Reduction Technique For SRAM Design

DOI

10.2991/cmfe-15.2015.202How to use a DOI?

Keywords

component; SRAM; Leakage current reduction (LCR); Optimization

Abstract

An optimization scheme of the leakage current reduction (LCR) for SRAM design has been proposed in this letter. By choosing the enabling signals for the LCR circuits intentionally, it can be deduced theoretically that there exists an optimal design option for the LCR technique application under the premise of SRAM performance re-quirement. Assuming that the reliably of SA sense requires 100mV differential voltage of bitlines, and the number of bitcells attached to one bitline is 2048, the simulate results shows that the discharging rate under the value of 256 of k is the fastest which is conform to the theoretical calculation, which means the most significant reduction of leakage current.

Copyright

© 2015, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - Fengyi Shang
AU  - Chunyu Peng
PY  - 2015/07
DA  - 2015/07
TI  - The Optimization Scheme Of The Leakage Current Reduction Technique For SRAM Design
BT  - Proceedings of the International Conference on Chemical, Material and Food Engineering
PB  - Atlantis Press
SP  - 908
EP  - 911
SN  - 2352-5401
UR  - https://doi.org/10.2991/cmfe-15.2015.202
DO  - 10.2991/cmfe-15.2015.202
ID  - Shang2015/07
ER  -