Proceedings of the 2018 International Conference on Computer Science, Electronics and Communication Engineering (CSECE 2018)

A Probability Model of Calculating L2 Cache Misses

Authors
Kecheng Ji, Ming Ling, Li Liu
Corresponding Author
Kecheng Ji
Available Online February 2018.
DOI
https://doi.org/10.2991/csece-18.2018.71How to use a DOI?
Keywords
probability model; stack distance; reuse distance; L2 cache misses
Abstract
Stack or reuse distances have been widely adopted in studying memory localities and cache behaviors. However, the memory references, normally profiled by a binary instru-mentation tool, only reflect the accessing sequence of instruction fetching and load or store executions. That is why the stack or the reuse distances obtained from these memory references cannot be used to predict the L2 or lower cache misses. This paper proposes a probability model to calculate the L2 reuse distance histogram from the L1 stack distance histograms without any extra simulations. The L2 cache misses or memory localities can be predicted fast and accurately based on the result of our model. We use 13 benchmarks chosen from Mobybench 2.0 and SPEC 2006 to evaluate the accuracy of our model. With the support of StatCache and StatStack, the average absolute error of modeling the L2 cache misses is about 8%. Meanwhile, contrast to gem5 fast simulations, the process of predicting L2 cache misses can be sped up by 50 times on average.
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This is an open access article distributed under the CC BY-NC license.

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Proceedings
2018 International Conference on Computer Science, Electronics and Communication Engineering (CSECE 2018)
Part of series
Advances in Computer Science Research
Publication Date
February 2018
ISBN
978-94-6252-487-3
ISSN
2352-538X
DOI
https://doi.org/10.2991/csece-18.2018.71How to use a DOI?
Open Access
This is an open access article distributed under the CC BY-NC license.

Cite this article

TY  - CONF
AU  - Kecheng Ji
AU  - Ming Ling
AU  - Li Liu
PY  - 2018/02
DA  - 2018/02
TI  - A Probability Model of Calculating L2 Cache Misses
BT  - 2018 International Conference on Computer Science, Electronics and Communication Engineering (CSECE 2018)
PB  - Atlantis Press
SN  - 2352-538X
UR  - https://doi.org/10.2991/csece-18.2018.71
DO  - https://doi.org/10.2991/csece-18.2018.71
ID  - Ji2018/02
ER  -