Proceedings of the 3rd International Conference on Material, Mechanical and Manufacturing Engineering

A Novel Clock circuit used in Time-Interleaved ADC

Authors
Xiaofeng Shen, Liang Li, Mingyuan Xu, Xi Chen
Corresponding Author
Xiaofeng Shen
Available Online August 2015.
DOI
https://doi.org/10.2991/ic3me-15.2015.178How to use a DOI?
Keywords
A/D converter, T-I ADC, Clock, Timing mismatch.
Abstract
This paper presents a new type of clock system based on standard CMOS 0.18 m, 1.8V process. It can be used for 14bit, 500 MHz sampling frequency, time interleaving (TI) ADC. The clock edge reassignment technique has been introduced in this paper. Simulation has been run in Spectre under Cadence platform. The result shows that this clock circuit is especially useful in a 14bit, 500MHz sampling frequency high speed TI ADC and the timing mismatch is less than roughly 2ps , which meets the design requirement.
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This is an open access article distributed under the CC BY-NC license.

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Proceedings
3rd International Conference on Material, Mechanical and Manufacturing Engineering (IC3ME 2015)
Part of series
Advances in Engineering Research
Publication Date
August 2015
ISBN
978-94-6252-100-1
ISSN
2352-5401
DOI
https://doi.org/10.2991/ic3me-15.2015.178How to use a DOI?
Open Access
This is an open access article distributed under the CC BY-NC license.

Cite this article

TY  - CONF
AU  - Xiaofeng Shen
AU  - Liang Li
AU  - Mingyuan Xu
AU  - Xi Chen
PY  - 2015/08
DA  - 2015/08
TI  - A Novel Clock circuit used in Time-Interleaved ADC
BT  - 3rd International Conference on Material, Mechanical and Manufacturing Engineering (IC3ME 2015)
PB  - Atlantis Press
SN  - 2352-5401
UR  - https://doi.org/10.2991/ic3me-15.2015.178
DO  - https://doi.org/10.2991/ic3me-15.2015.178
ID  - Shen2015/08
ER  -