Power Macro Modelling for CMOS Inverter of 0.12 um Technology
Authors
Shahzad Naseem, Saira Riaz, Muhammad Azam, Syed S. Ali, Yaseer A. Durrani
Corresponding Author
Shahzad Naseem
Available Online August 2013.
- DOI
- 10.2991/icacsei.2013.124How to use a DOI?
- Keywords
- CMOS inverter, Power consumption, load capacitance, parasitic capacitance
- Abstract
Power dissipation of very large scale integrated circuits (VLSI) has emerged as a significant constraint on the semiconductor industry. For dynamic power the voltage, capacitance and frequency are the major components of power dissipation. In this paper, we propose a power macro modelling technique for the CMOS inverter using 0.12µm technology. The dynamic power is directly linked with the load capacitance (CL), and it is lumped as all internal parasitic capacitances. In our modelling, we take account of the parasitic capacitances with their dependence on channel length and width. Suitable values of other factors (i.e. threshold voltage VT, gate voltage VGS, drain voltage VDD etc.) are used for power consumption of the CMOS inverter.
- Copyright
- © 2013, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Shahzad Naseem AU - Saira Riaz AU - Muhammad Azam AU - Syed S. Ali AU - Yaseer A. Durrani PY - 2013/08 DA - 2013/08 TI - Power Macro Modelling for CMOS Inverter of 0.12 um Technology BT - Proceedings of the 2013 International Conference on Advanced Computer Science and Electronics Information (ICACSEI 2013) PB - Atlantis Press SP - 509 EP - 513 SN - 1951-6851 UR - https://doi.org/10.2991/icacsei.2013.124 DO - 10.2991/icacsei.2013.124 ID - Naseem2013/08 ER -