Cyclic Redundancy Check: A Novel Software Implementation for machine cycle optimization and analysis for deciding Low Peak to Average Power Ratio Discrete Sequences

DOI

10.2991/iccasp-16.2017.66How to use a DOI?

Keywords

Cyclic Redundancy Check (CRC), Look- Up Table (LUT), Machine Cycles, Peak to Average Power Ratio (PAPR), Optimi-zation.

Abstract

Cyclic Redundancy Check (CRC) is widely used error detection technique in many contemporary communication systems such as Fourth Generation (4G) Mobile Communication-Long Term Evolution (LTE) and LTE Ad-vanced, Wi-Fi, Wireless LAN. For real time embedded systems, code size (Memory), Processor Machine Cycle (Speed) and Power are the three important parameters which are needs to be optimized. CRC is very effective and simple for error detection but its software implementation is not efficient. This paper presents software im-plementation of CRC using Bit by Bit (BYB) and Look-Up Table (LUT) approaches reported in the earlier liter-ature. Using these approaches, we have compared machine cycle requirements for computation of CRC-3/5/8/12/16 generator polynomials. We have used TMS320C6713 and Freescale Star Core SC140 architectures for comparing the machine cycle requirements. Then we have intuitively modified our software implementa-tions (Based on C program) of LUT using In Place Computation (IPC).This IPC-LUT based CRC computation is found to be more optimized in terms of machine cycle and memory compared to LUT method. We have re-duced the machine cycle requirement by 39.47 % using our IPC-LUT approach compared to conventional LUT. We have also developed inline assembly code for SC140 architecture using IPC-LUT approach that takes only 45 machine cycles for computations. Peak to Average Power Ratio (PAPR) is one of the major drawback of contemporary communication systems. For third parameter (Power), we have simply done the analysis to fix up the decision criteria for deciding the sequences having low PAPR.

Copyright

© 2017, the Authors. Published by Atlantis Press.

Open Access

This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).

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TY  - CONF
AU  - A. Kotade
AU  - A. Nandgaonkar
AU  - S. Nalbalwar
AU  - U. Shivurkar
PY  - 2016/12
DA  - 2016/12
TI  - Cyclic Redundancy Check: A Novel Software Implementation for machine cycle optimization and analysis for deciding Low Peak to Average Power Ratio Discrete Sequences
BT  - Proceedings of the International Conference on Communication and Signal Processing 2016 (ICCASP 2016)
PB  - Atlantis Press
SP  - 438
EP  - 446
SN  - 1951-6851
UR  - https://doi.org/10.2991/iccasp-16.2017.66
DO  - 10.2991/iccasp-16.2017.66
ID  - Kotade2016/12
ER  -