An Optimized VLSI Architecture For High-Performance Real-Time Video Processing

DOI

10.2991/978-94-6463-858-5_201How to use a DOI?

Keywords

Edge detection techniques; Sobel Operator; Prewitt Operator; FPGA

Abstract

Most video processing applications, including surveillance, object detection, and scene comprehension, rely on edge detection. Real-time video data processing requires efficient hardware that meets the demands of edge detection algorithms with minimal power usage. High-speed edge detection and resource efficiency coexist harmoniously in the proposed design, employing data flow optimization and parallel computation to improve speed. Memory management and data buffering are also optimized to ensure seamless video processing. The architecture is implemented using the Artix-7 FPGA, based on Canny edge detection algorithms. This paper discusses the system's design, implementation, and experimental results, highlighting its performance compared to conventional approaches.

Copyright

© 2025 The Author(s)

Open Access

Open Access This chapter is licensed under the terms of the Creative Commons Attribution-NonCommercial 4.0 International License (http://creativecommons.org/licenses/by-nc/4.0/), which permits any noncommercial use, sharing, adaptation, distribution and reproduction in any medium or format, as long as you give appropriate credit to the original author(s) and the source, provide a link to the Creative Commons license and indicate if changes were made.

Download article (PDF)

TY  - CONF
AU  - Lakkakula Sannidhi
AU  - S. V. S. Prasad
AU  - Manoj Kumar
PY  - 2025
DA  - 2025/11/04
TI  - An Optimized VLSI Architecture For High-Performance Real-Time Video Processing
BT  - Proceedings of International Conference on Computer Science and Communication Engineering (ICCSCE 2025)
PB  - Atlantis Press
SP  - 2410
EP  - 2420
SN  - 2352-538X
UR  - https://doi.org/10.2991/978-94-6463-858-5_201
DO  - 10.2991/978-94-6463-858-5_201
ID  - Sannidhi2025
ER  -