A UVM-based AES IP Verification Platform with Automatic Testcases
- https://doi.org/10.2991/iceat-16.2017.91How to use a DOI?
This paper applied UVM (Universal Verification Methodology), an advanced verification methodology which was based on SystemVerilog language to build AES (Advanced Encryption Standard) IP verification platform and environment. Functional verification of the AES module, through a large number of testcases and constrained random test could achieve 100% functional coverage. In addition, the testcases will be run by the verification platform with automatic generation. It both can run the specified testcases in the terminal, which can customize the testcases variables through the orientation test method, and can automatically run all the testcases of the verification platform. This method could improve the efficiency and reusability of the verification, and the simulation results show that the AES IP design is successful.
- © 2017, the Authors. Published by Atlantis Press.
- Open Access
- This is an open access article distributed under the CC BY-NC license (http://creativecommons.org/licenses/by-nc/4.0/).
Cite this article
TY - CONF AU - Lin Zhu AU - Ligang Hou AU - Qiuyun Xu AU - Jingsong Zhi AU - Jinhui Wang PY - 2016/05 DA - 2016/05 TI - A UVM-based AES IP Verification Platform with Automatic Testcases BT - Proceedings of the 2016 International Conference on Engineering and Advanced Technology PB - Atlantis Press SP - 442 EP - 448 SN - 2352-5401 UR - https://doi.org/10.2991/iceat-16.2017.91 DO - https://doi.org/10.2991/iceat-16.2017.91 ID - Zhu2016/05 ER -